1. Field of the Invention
The present invention generally relates to the design and fabrication of transistors suitable for high density integration and, more particularly, to transistors capable of high performance even when operated at reduced voltages, such as in integrated circuits for portable devices.
2. Description of the Prior Art
The possibility of increased chip functionality and performance and economy of manufacture of integrated circuits has provided substantial pressure toward higher integration density of integrated circuits. By the same token, greater chip functionality has also led to the development of many portable devices of small size such as so-called personal digital assistants, portable telephones with enhanced (e.g. video) functions and the like. However, portable devices must have power supplies which do not significantly compromise the quality of portability, such as by the size and/or weight of batteries. Therefore, a severe constraint is placed on power consumption of the integrated circuits and the transistors therein to provide adequate periods of service of the portable devices between battery replacement or recharging.
Even in non-portable devices, increased integration density is accompanied by increased power dissipation density. Even though power dissipated by a single transistor may seem quite small, the power consumption or dissipation per unit of chip area increases with integration density. Moreover, power dissipation per transistor increases with switching frequency/clock rate; increased clock rate being a major incentive for increased integration density by reduction of signal propagation path length as well as reduced noise susceptibility.
The most common approach to reduction of power consumption has been to scale power supplies to lower voltages while maintaining sufficient voltage overdrive capability to maintain acceptable switching speed of transistors. In particular, while field effect transistors (e.g. MOSFETs) have become the technology of choice for all but the highest switching speeds, the transition time between “on” and “off” states, sometimes referred to as the slew rate, is severely degraded as power supply voltage is reduced; largely because of the capacitive load presented by field effect transistor gates. While field effect transistors can be designed to operate satisfactorily at voltages which are somewhat reduced, they cannot be scaled to lower voltages as readily as power supplies. In particular, the threshold voltage cannot be scaled by the same amount as power supply voltage because of sub-threshold leakage and the low limit for the sub-threshold output voltage swing. Additionally, scaling of MOSFETs may cause them to be more delicate and susceptible to damage from breakdown due to static charge, coupled noise and the like. Accordingly, it is an extreme challenge to scale the power supply voltage, improve the circuit speed and limit the leakage current simultaneously.
Dynamic threshold voltage MOSFETs (DTMOSFETs) are known and an exemplary design is disclosed in U.S. Pat. No. 5,559,368. A schematic depiction of this transistor is illustrated in FIG. 1. This transistor design seeks to maintain high performance at reduced power supply voltage by connecting the gate of the transistor to the silicon well in which the transistor is formed and can achieve a high drive current in the “on” state as well as low “off” state leakage current. In the “off” state, Vgs=Vbs=0V and the transistor has a high threshold. In the “on” state, Vgs=Vds=Vbs and has a low threshold because gate voltage is applied to the body of the transistor. However, the principal disadvantage of this transistor design is that because gate bias is applied to the transistor body, the leakage current of the forward biased p-n junction at the source increases dramatically when the power supply voltage is greater than 0.7 V; effectively limiting the power supply voltage to that value; a value which increases noise susceptibility and does not support sufficient voltage overdrive for optimal or potential switching speed.